1. Field of the Invention
The present invention relates to a method for forming isolation regions and, more particularly, to a method of poly-buffered local oxidation of silicon isolation.
2. Description of the Prior Art
For building an integrated circuit operating with desired action, it is necessary to fabricate many active devices on a single semiconductor substrate. Various kinds of devices with different functions, such as transistors, resistors and capacitors, are formed together. Each of the devices on the substrate must be electrically isolated from the others to ensure their individual function. The art of isolating semiconductor devices becomes one important aspect of modern metal-oxide-semiconductor (MOS) and bipolar integrated circuit technology for the separation of different devices or different functional regions. With the high integration of the semiconductor devices, improper isolation among devices will cause current leakage and the current leakage can consume a significant amount of power. Improper isolation will result in circuit latch-up, which can destroy the circuit temporarily or even permanently. In addition, improper isolation can cause degradation in circuit noise margin, voltage shift and crosstalk.
Local oxidation of silicon (LOCOS) is one of the most well-known techniques for isolation. LOCOS provides the isolation by oxidizing the silicon substrate to create silicon dioxide regions among active devices or functional regions. Because it is easy for the silicon substrate to be oxidized into silicon dioxide, LOCOS has the benefits of its process simplicity and low cost, and has become the most widely used isolation technique in very large scale integrated (VLSI) circuit. However, with the tendency for the manufacture of semiconductor integral circuit to high package density, LOCOS meets the limitation in its scalability.
In the paper "Characteristics of CMOS Device Isolation for the ULSI Age" in IEDM Tech. Dig., p. 671, 1994, by A. Bryant, et al., the two different isolation techniques of LOCOS and STI are investigated. The paper reviews how LOCOS and STI isolations are being improved to meet the scaling requirements for abrupt active-isolation transitions, isolation depth, and isolation planarity. For deep sub-micron CMOS generation, the conventional LOCOS isolation suffers from several drawbacks such as the large lateral extent of bird's beak, non-planarity, local field oxide thinning effect, and stress-induced silicon defects. The key challenges to LOCOS scaling are insulator thinning at narrow dimension, bird's beak formation, and field-implant encroachment. For future CMOS technology, an effective device isolation method that provides abrupt transitions to active device regions with minimum impact on device characteristics or topography will be required.
The main issue of the LOCOS is the unavoidable lateral oxidation of silicon under the masking nitride layer, which narrows the active device area and is often referred to as the "bird's beak". In order to suppress the lateral diffusion of oxidants for reducing the bird's beak, the pad oxide layer should be thinned to a minimum thickness. A polysilicon layer has been employed to be a buffered layer instead of pad oxide for optimization between nitride stress relief and pad oxide thinning. Polysilicon-buffered LOCOS is therefore developed to be an improved method for conventional LOCOS to suppress the lateral bird's beak. As described by T. Nishihara, et al., in their paper titled "A 0.5 .mu.m Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL)", IEDM Tech. Dig., p. 100, 1988, the PBLOCOS simply use a polysilicon layer to take over the buffered function of pad oxide. The effect of bird's beak can thus be reduced as the thickness of the pad oxide layer is minimized.
Although it can reduce the bird's beak effect, the PBLOCOS still encounter some problems such as the pitting formation, which is mentioned by J. Nagel, et al., in the paper "Stress-Induced Void Formation in Interlevel Polysilicon Film during Polybuffered Local Oxidation of Silicon", J. Electrochem. Soc., vol. 140, p. 2356, 1993. During the wet etching process to form the masking nitride layer by hot phosphoric acid, the etchant also attacks the underlying polysilicon in the vicinity of the field oxide. This results in damages to the substrate. The pit formation is also found in the buffer polysilicon after wet nitride removal and in silicon substrate after polysilicon etching. It is attributed to a chemical reaction of water, ammonia, and silicon during wet field oxidation, similar to the so-called white-ribbon effect. The mechanism of this reaction is investigated by T. T. Sheng, et al., in the paper "From White Ribbon to Black Belt: A Direct Observation of the Kooi Effect Masking Film by Transmission Electron Microscopy", J. Electrochem. Soc., vol. 140, p. L.163, 1993. This mechanism induces damages to the substrate and results in yield loss in deep submicron devices, which is what the present invention tries to avoid.